The present disclosure relates to a data reproduction circuit to which data is input via e.g. a transmission line and a data transmission device using the data reproduction circuit.
The serial data transmission is excellent in space saving because a signal can be transmitted by one or a pair of transmission media. Furthermore, it is free from a problem of skew between data (timing deviation) occurring when a signal is transmitted by a multi-core signal transmission line and therefore is suitable for long-distance data transmission.
In Japanese Patent Laid-open No. Hei 10-145436 and Japanese Patent Laid-open No. Hei 11-98130 (hereinafter, Patent Documents 1 and 2), a data transmission device that simultaneously transmits downstream data and a reference clock request signal that is an upstream common-mode signal is described.
According to this data transmission device, simplification of the circuit configuration and space saving of the transmission line are achieved and a wide range of the data transmission rate can be covered. Thus, the data transmission device has an advantage of being capable of realizing high-speed data transmission and transmission of the reference clock request signal with a simple circuit configuration.
This data transmission device is provided with a data reproduction circuit that detects the upstream common-mode signal transmitted via the transmission line and reproduces data in accordance with the result of comparison between the detected signal and a reference voltage in a comparator.
FIG. 1 is a diagram showing a general configuration example of the data reproduction circuit using a comparator.
FIG. 2 is a timing chart of the data reproduction circuit of FIG. 1.
A data reproduction circuit 1 of FIG. 1 is configured by a comparator 2 to which an input voltage (data) VIN and a reference voltage VREF are input.